A semiconductor memory device typically includes an array of memory cells arranged in rows and columns, with each memory cell configured to store one or more bits of data. The memory cells within a given row of the array are coupled to a common wordline, while the memory cells within a given column of the array are coupled to a common bitline. Thus, the array includes a memory cell at each point where a wordline intersects with a bitline. Reading a given memory cell generally comprises transferring data stored within that cell to its corresponding bitline, and writing a given memory cell generally comprises transferring data into that cell from its corresponding bitline. Such read and write operations to the given memory cell occur in conjunction with an assertion of its corresponding wordline.
Memory devices of the type described above may each include one or more memory ports. For example, a single-port random access memory (SPRAM) includes a single memory port and only a single read or write access can be done at a given time through this port. A dual-port random access memory (DPRAM) has two independent memory ports, such that read or write accesses can be performed simultaneously and independently through each port.
A conventional SPRAM may be a static memory device formed using six-transistor (6T) static RAM (SRAM) memory cells. A given such SRAM memory cell may include, for example, two NMOS pass gate transistors and a pair of cross-coupled inverters, with the two inverters collectively comprising two PMOS pull-up transistors and two NMOS pull-down transistors. One known approach to implementing a DPRAM involves utilizing a more complex eight-transistor (8T) SRAM memory cell in place of the 6T memory cell used in the SPRAM. However, since the number of memory cells in the array is typically very large, use of the more complex 8T memory cell has a significant negative impact on the overall circuit area and power requirements of the resulting DPRAM device.
It is therefore apparent that a need exists for an improved approach to implementing DPRAMs and other multiple-port memory devices.